Regviz

Cypress Semiconductor /psoc63 /CPUSS /TRIM_RAM_CTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TRIM_RAM_CTL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/CPUSS/TRIM_RAM_CTL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RM0 (RME)RME 0WPULSE 0RA0WA

Description

RAM trim control

Fields

RM

N/A
RME

Read-Write margin enable control. This selects between the default Read-Write margin setting, and the external RM[3:0] Read-Write margin settting.
WPULSE

Write Assist Pulse to control pulse width of negative voltage on SRAM bitline.
RA

Read Assist control for WL under-drive.
WA

Write assist enable control (Active High).

  • WA[1:0] Write Assist pins to control negative voltage on SRAM bitline.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data